C8051F02X Datasheet, PDF (223/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 21.8. SCON1: UART1 Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SM01/FE1 SM11/RXOV1 SM21/TXCOL1 REN1 TB81 RB81 TI1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W Reset Value
RI1 00000000
Bit0 SFR Address:
0xF1
Bits7-6:
The function of these bits is determined by the SSTAT1 bit in register PCON.
If SSTAT1 is logic 1, these bits are UART1 status indicators as described in Section 21.3.
If SSTAT1 is logic 0, these bits select the Serial Port Operation Mode as shown below.
SM01-SM11: Serial Port Operation Mode:
SM01
0
0
1
1
SM11
0
1
0
1
Mode
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM21: Multiprocessor Communication Enable.
If SSTAT1 is logic 1, this bit is a UART1 status indicator as described in Section 21.3.
If SSTAT1 is logic 0, the function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
Modes 2 and 3: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1 and the received
address matches the UART1 address or the broadcast address.
REN1: Receive Enable.
This bit enables/disables the UART1 receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used
in Modes 0 and 1. Set or cleared by software as required.
RB81: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM21 is
logic 0, RB81 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in Mode 0, or
at the beginning of the stop bit in other modes). When the UART1 interrupt is enabled, setting this bit
causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually
by software
RI1: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART1 (as selected by the SM21 bit).
When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 inter-
rupt service routine. This bit must be cleared manually by software.
Rev. 1.4
223