C8051F02X Datasheet, PDF (246/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.3.3. Mode 2: Baud Rate Generator
Timer 4 can be used as a baud rate generator for UART1 when UART1 is operated in modes 1 or 3 (refer to Section
“21.1. UART1 Operational Modes” on page 216 for more information on the UART1 operational modes). In Baud
Rate Generator mode, Timer 4 works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two
capture registers (RCAP4H, RCAP4L) is automatically loaded into the counter/timer register. However, the TF4
overflow flag is not set and no interrupt is generated. Instead, the overflow event is used as the input to the UART's
shift clock. Timer 4 overflows can be selected to generate baud rates for transmit and/or receive independently.
The Baud Rate Generator mode is selected by setting RCLK1 (T4CON.5) and/or TCLK1 (T4CON.4) to ‘1’. When
RCLK1 or TCLK1 is set to logic 1, Timer 4 operates in the auto-reload mode regardless of the state of the CP/RL4
bit. Note that in Baud Rate Generator mode, the Timer 4 timebase is the system clock divided by two. When selected
as the UART1 baud clock source, Timer 4 defines the UART1 baud rate as follows:
Baud Rate = SYSCLK / ((65536 - [RCAP4H, RCAP4L] ) * 32)
If a different time base is required, setting the C/T4 bit to logic 1 will allow the timebase to be derived from the exter-
nal input pin T4. In this case, the baud rate for the UART is calculated as:
Baud Rate = F_CLK / ( (65536 - [RCAP4H, RCAP4L] ) * 16)
Where F_CLK is the frequency of the signal (TCLK) supplied to Timer 4 and [RCAP4H, RCAP4L] is the 16-bit value
held in the capture registers.
As explained above, in Baud Rate Generator mode, Timer 4 does not set the TF4 overflow flag and therefore cannot
generate an interrupt. However, if EXEN4 is set to logic 1, a high-to-low transition on the T4EX input pin will set the
EXF4 flag and a Timer 4 interrupt will occur if enabled. Therefore, the T4EX input may be used as an additional
external interrupt source.
Figure 22.27. T4 Mode 2 Block Diagram
C/T2
SYSCLK
2
0
T2
Crossbar 1
TCLK
TL2
RCLK0
Timer 2
Overflow
TH2
0
TR2
PCON
S
M
O
D
0
SI
TD
OL
PE
Reload
RCAP2L RCAP2H
16
1
0
Timer 1
Overflow
2
0
1
T2EX
EXEN2
Crossbar
CP/RL2
C/T2
TR2
EXEN2
TCLK0
RCLK0
EXF2
TF2
Interrupt
16
1
TCLK0
RX0 Clock
TX0 Clock
246
Rev. 1.4