MC68HC812A4 Datasheet, PDF (86/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Operating Modes and Resource Mapping
ESTR — E-Clock Stretch Enable Bit
ESTR determines if the E-clock behaves as a simple free-running
clock or as a bus control signal that is active only for external bus
cycles.
1 = E stretches high during external access cycles and low during
non-visible internal accesses.
0 = E never stretches (always free running).
Normal modes: Write once
Special modes: Write anytime
IVIS — Internal Visibility Bit
IVIS determines whether internal ADDR, DATA, R/W, and LSTRB
signals can be seen on the external bus during accesses to internal
locations. If this bit is set in special narrow mode and EMD = 1 when
an internal access occurs, the data appears wide on port C and port
D. This allows for emulation. Visibility is not available when the part is
operating in a single-chip mode.
1 = Internal bus operations are visible on external bus.
0 = Internal bus operations are not visible on external bus.
Normal modes: Write once
Special modes: Write anytime except the first time
EMD — Emulate Port D Bit
This bit only has meaning in special expanded narrow mode.
In expanded wide modes and special peripheral mode, PORTD,
DDRD, KWIED, and KWIFD are removed from the memory map
regardless of the state of this bit.
In single-chip modes and normal expanded narrow mode, PORTD,
DDRD, KWIED, and KWIFD are in the memory map regardless of the
state of this bit.
1 = If in special expanded narrow mode, PORTD, DDRD, KWIED,
and KWIFD are removed from the memory map. Removing the
registers from the map allows the user to emulate the function
of these registers externally.
0 = PORTD, DDRD, KWIED, and KWIFD are in the memory map.
Normal modes: Write once
Special modes: Write anytime except the first time
MC68HC812A4 — Rev. 3.0
86
Operating Modes and Resource Mapping
Advance Information
MOTOROLA