MC68HC812A4 Datasheet, PDF (244/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Communications Interface Module (SCI)
For an 8-bit data character, data sampling of the stop bit takes the
receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 14-13, the receiver
counts 154 RT cycles at the point when the count of the transmitting
device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit data character with no errors is:
-1---5---4--1---5^–---4--1---4---7-- ^{× 100 = 4.54%}
For a 9-bit data character, data sampling of the stop bit takes the
receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 14-13, the receiver
counts 170 RT cycles at the point when the count of the transmitting
device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is:
-1---7---0--1---7^–---0--1---6---3-- ^{× 100 = 4.12%}
Fast Data Tolerance
Figure 14-14 shows how much a fast received frame can be misaligned
without causing a noise error or a framing error. The fast stop bit ends at
RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
STOP
IDLE OR NEXT FRAME
DATA
SAMPLES
Figure 14-14. Fast Data
MC68HC812A4 — Rev. 3.0
244
Serial Communications Interface Module (SCI)
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