MC68HC812A4 Datasheet, PDF (74/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Resets and Interrupts
4.5.2 Highest Priority I Interrupt Register
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read: 1
Write:
1
0
PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
Reset: 1
1
1
1
0
0
1
0
= Unimplemented
Figure 4-2. Highest Priority I Interrupt Register (HPRIO)
Read: Anytime
Write: Only if I mask in CCR = 1 (interrupts inhibited)
To give a maskable interrupt source highest priority, write the low byte
of the vector address to the HPRIO register. For example, writing $F0 to
HPRIO assigns highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an unimplemented vector address or a
non-I-masked vector address (a value higher than $F2) is written, then
IRQ is the default highest priority interrupt.
4.6 Resets
There are five possible sources of reset. Power-on reset (POR), external
reset on the RESET pin, and reset from the alternate reset pin, ARST,
share the normal reset vector. The computer operating properly (COP)
reset and the clock monitor reset each has a vector. Entry into reset is
asynchronous and does not require a clock but the MCU cannot
sequence out of reset without a system clock.
4.6.1 Power-On Reset
A positive transition on V_DD causes a power-on reset (POR). An external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
MC68HC812A4 — Rev. 3.0
74
Resets and Interrupts
Advance Information
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