MC68HC812A4 Datasheet, PDF (170/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Phase-Lock Loop (PLL)
11.4 Register Map
Addr.
Register Name
Bit 7
6
5
Read: 0
0
0
Loop Divider Register
$0040
High (LDVH) Write:
See page 171.
Reset: 0
0
0
$0041
Loop Divider Register
Low (LDVL)
See page 171.
Read:
Write:
Reset:
LDV7
1
LDV6
1
LDV5
1
Read: 0
0
0
Reference Divider
$0042 Register High (RDVH) Write:
See page 172.
Reset: 0
0
0
$0043
Reference Divider
Register Low (RDVL)
See page 172.
Read:
Write:
Reset:
RDV7
1
RDV6
1
RDV5
1
$0047
Clock Control Register
(CLKCTL)
See page 173.
Read:
Write:
Reset:
LCKF
0
PLLON
0
PLLS
0
= Unimplemented
4
3
0
LDV11
0
1
LDV4 LDV3
1
1
0
RDV11
0
1
RDV4 RDV3
1
1
BCSC BCSB
0
0
Figure 11-2. PLL Register Map
2
LDV10
1
LDV2
1
RDV10
1
RDV2
1
BCSA
0
1
LDV9
1
LDV1
1
RDV9
1
RDV1
1
MCSB
0
Bit 0
LDV8
1
LDV0
1
RDV8
1
RDV0
1
MCSA
0
11.5 Functional Description
The PLL may be used to run the MCU from a different timebase than the
incoming crystal value. If the PLL is selected, it continues to run when
it’s in wait or stop mode which results in more power consumption than
normal. To take full advantage of the reduced power consumption of
stop mode, turn off the PLL before going into stop.
Although it is possible to set the divider to command a very high clock
frequency, do not exceed the 16.8 MHz frequency limit for the MCU.
MC68HC812A4 — Rev. 3.0
170
Phase-Lock Loop (PLL)
Advance Information
MOTOROLA