MC68HC812A4 Datasheet, PDF (44/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
2.3 Register Map
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Register Name
Port A Data Register
(PORTA)
See page 96.
Port B Data Register
(PORTB)
See page 97.
Port A Data Direction
Register (DDRA)
See page 96.
Port B Data Direction
Register (DDRB)
See page 97.
Port C Data Register
(PORTC)
See page 98.
Port D Data Register
(PORTD)
See page 100.
Port C Data Direction
Register (DDRC)
See page 99.
Port D Data Direction
Register (DDRD)
See page 101.
Port E Data Register
(PORTE)
See page 102.
Port E Data Direction
Register (DDRE)
See page 103.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
PA7
0
PB7
0
DDRA7
0
DDRB7
0
PC7
0
PD7
0
DDRC7
0
Bit 7
0
PE7
0
DDRE7
0
6
5
PA6
PA5
0
0
PB6
PB5
0
0
DDRA6 DDRA5
0
0
DDRB6 DDRB5
0
0
PC6
PC5
0
0
PD6
PD5
0
0
DDRC6 DDRC5
0
0
Bit 6
Bit 5
0
0
PE6
PE5
0
0
DDRE6 DDRE5
0
0
= Unimplemented
4
3
2
1
Bit 0
PA4
PA3
PA2
PA1
PA0
0
0
0
0
0
PB4
PB3
PB2
PB1
PB0
0
0
0
0
0
DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
PC4
PC3
PC2
PC1
PC0
0
0
0
0
0
PD4
PD3
PD2
PD1
PD0
0
0
0
0
0
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
PD4
PD3
PD2
PD1
PD0
0
1
0
0
0
DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
1
1
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 1 of 15)
MC68HC812A4 — Rev. 3.0
44
Register Block
Advance Information
MOTOROLA