MC68HC812A4 Datasheet, PDF (185/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Standard Timer Module
Functional Description
12.5.4.1 Event Counter Mode
Clearing the PAMOD bit configures the PA for event counter operation.
An active edge on the PAI pin increments the PA. The PA edge bit,
PEDGE, selects falling edges or rising edges to increment the PA.
An active edge on the PAI pin sets the PA input flag, PAIF. The PA input
interrupt enable bit, PAI, enables the PAIF flag to generate interrupt
requests.
NOTE:
The PAI input and timer channel 7 use the same pin. To use the PAI
input, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7
output compare 7 mask bit, OC7M7.
The PA counter registers, TIMPACNTH/L, reflect the number of active
input edges on the PAI pin since the last reset.
The PA overflow flag, PAOVF, is set when the PA rolls over from $FFFF
to $0000. The PA overflow interrupt enable bit, PAOVI, enables the
PAOVF flag to generate interrupt requests.
NOTE: The PA can operate in event counter mode even when the timer enable
bit, TE, is clear.
12.5.4.2 Gated Time Accumulation Mode
Setting the PAMOD bit configures the PA for gated time accumulation
operation. An active level on the PAI pin enables a divided-by-64 clock
to drive the PA. The PA edge bit, PEDGE, selects low levels or high
levels to enable the divided-by-64 clock.
The trailing edge of the active level at the PAI pin sets the PA input flag,
PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to
generate interrupt requests.
NOTE:
The PAI input and timer channel 7 use the same pin. To use the PAI
input, disconnect it from the output logic by clearing the channel 7 output
mode and output level bits, OM7 and OL7. Also clear the channel 7
output compare mask bit, OC7M7.
Advance Information
MOTOROLA
Standard Timer Module
MC68HC812A4 — Rev. 3.0
185