MC68HC812A4 Datasheet, PDF (306/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

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17.3 Instruction Queue
The CPU12 instruction queue provides at least three bytes of program
information to the CPU when instruction execution begins. The CPU12
always completely finishes executing an instruction before beginning to
execute the next instruction. Status signals IPIPE[1:0] provide
information about data movement in the queue and indicate when the
CPU begins to execute instructions. This makes it possible to monitor
CPU activity on a cycle-by-cycle basis for debugging. Information
available on the IPIPE[1:0] pins is time multiplexed. External circuitry
can latch data movement information on rising edges of the E-clock
signal; execution start information can be latched on falling edges.
Table 17-1 shows the meaning of data on the pins.
Table 17-1. IPIPE Decoding
Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock⁽¹⁾
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No movement
0:1
LAT
Latch data from bus
1:0
ALD
Advance queue and load from bus
1:1
ALL
Advance queue and load from latch
Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock⁽²⁾
IPIPE[1:0]
Mnemonic
Meaning
0:0
—
No start
0:1
INT
Start interrupt sequence
1:0
SEV
Start even instruction
1:1
SOD
Start odd instruction
1. Refers to data that was on the bus at the previous E falling edge.
2. Refers to bus cycle starting at this E falling edge.
MC68HC812A4 — Rev. 3.0
306
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