MC68HC812A4 Datasheet, PDF (237/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Communications Interface Module (SCI)
Functional Description
14.6.4.1 Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters.
The state of the M bit in SCI control register 1 (SCCR1) determines the
length of data characters. When receiving 9-bit data, bit R8 in SCI data
register high (SCDRH) is the ninth bit (bit 8).
14.6.4.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from
the RXD pin. The SCI data register is the read-only buffer between the
internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data
portion of the frame transfers to the SCI data register. The receive data
register full flag, RDRF, in SCI status register 1 (SCSR1) becomes set,
indicating that the received byte can be read. If the receive interrupt
enable bit, RIE, in SCI control register 2 (SCCR2) is also set, the RDRF
flag generates an interrupt request.
14.6.4.3 Data Sampling
The receiver samples the RXD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock (see Figure 14-6) is resynchronized:
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
Advance Information
MOTOROLA
Serial Communications Interface Module (SCI)
MC68HC812A4 — Rev. 3.0
237