MC68HC812A4 Datasheet, PDF (21/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

List of Figures
Figure
Title
Page
8-16
8-17
8-18
8-19
Chip-Select Control Register 0 (CSCTL0) . . . . . . . . . . . . . . .136
Chip-Select Control Register 1 (CSCTL1) . . . . . . . . . . . . . . .138
Chip-Select Stretch Register 0 (CSSTR0) . . . . . . . . . . . . . . .139
Chip-Select Stretch Register 1 (CSSTR1) . . . . . . . . . . . . . . .139
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . .144
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . .145
Port D Key Wakeup Interrupt Enable Register (KWIED) . . . .145
Port D Key Wakeup Flag Register (KWIFD). . . . . . . . . . . . . .146
Port H Data Register (PORTH). . . . . . . . . . . . . . . . . . . . . . . .146
Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . .147
Port H Key Wakeup Interrupt Enable Register (KWIEH) . . . .147
Port H Key Wakeup Flag Register (KWIFH). . . . . . . . . . . . . .148
Port J Data Register (PORTJ) . . . . . . . . . . . . . . . . . . . . . . . .148
Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . .149
Port J Key Wakeup Interrupt Enable Register (KWIEJ) . . . . .149
Port J Key Wakeup Flag Register (KWIFJ) . . . . . . . . . . . . . .150
Port J Key Wakeup Polarity Register (KPOLJ). . . . . . . . . . . .150
Port J Pullup/Pulldown Select Register (PUPSJ) . . . . . . . . . .151
Port J Pullup/Pulldown Enable Register (PULEJ). . . . . . . . . .152
10-1 Clock Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .154
10-2 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .155
10-3 Clock Function Register Map . . . . . . . . . . . . . . . . . . . . . . . . .156
10-4 Clock Chain for SCI0, SCI1, RTI, and COP . . . . . . . . . . . . . .158
10-5 Clock Chain for TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
10-6 Clock Chain for SPI, ATD and BDM . . . . . . . . . . . . . . . . . . . .160
10-7 Real-Time Interrupt Control Register (RTICTL) . . . . . . . . . . .161
10-8 Real-Time Interrupt Flag Register (RTIFLG) . . . . . . . . . . . . .163
10-9 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .163
10-10 Arm/Reset COP Timer Register (COPRST) . . . . . . . . . . . . . .166
11-1 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
11-2 PLL Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11-3 Loop Divider Register High (LDVH) . . . . . . . . . . . . . . . . . . . .171
Advance Information
MOTOROLA
List of Figures
MC68HC812A4 — Rev. 3.0
21