MC68HC812A4 Datasheet, PDF (174/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Phase-Lock Loop (PLL)
Table 11-2. Base Clock Selection
BCSC:BCSB:BCSA
SYSCLK
000
MUXCLK
001
M------U----X-2---C----L----K--
010
M------U----X--_{4--C----L----K--}
011
M------U----X--_{8--C----L----K--}
100
M------U----X_{1---6-C----L----K--}
101
M------U----X_{3---2-C----L----K--}
110
M------U----X_{6---4-C----L----K--}
111
M------U---_{1-X--2--C-8---L----K--}
MCSA and MCSB — Module Clock Select Bits
These bits determine the clock used by some sections of some of the
modules such as the baud rate generators of the SCIs, the timer
counter, the RTI, and COP. See Table 11-3. MCLK is the module
clock and PCLK is an internal bus rate clock.
Table 11-3. Module Clock Selection
MCS[B:A]
MCLK
00
PCLK
01
P_----C_--2---L_---K_--
10
P_----C_---4--L_---K_--
11
P_----C_---8--L_---K_--
The BCSx and MCSx bits can be changed with a single-write access. In
combination, these bits can be used to “throttle” the CPU clock rate
without affecting the MCLK rate; timing and baud rates can remain
constant as the processor speed is changed to match system
requirements. This can save overall system power.
MC68HC812A4 — Rev. 3.0
174
Phase-Lock Loop (PLL)
Advance Information
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