MC68HC812A4 Datasheet, PDF (70/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Resets and Interrupts
4.2 Introduction
Resets and interrupts are exceptions. Each exception has a 16-bit vector
that points to the memory location of the associated exception-handling
routine. Vectors are stored in the upper 128 bytes of the standard
64-Kbyte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
4.3 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
maskable. The remaining sources are maskable and any one of them
can be given priority over other maskable interrupts.
The priorities of the non-maskable sources are:
1. POR (power-on reset) or RESET pin
2. Clock monitor reset
3. COP (computer operating properly) watchdog reset
4. Unimplemented instruction trap
5. Software interrupt instruction (SWI)
6. XIRQ signal (if X bit in CCR = 0)
MC68HC812A4 — Rev. 3.0
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Resets and Interrupts
Advance Information
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