MC68HC812A4 Datasheet, PDF (172/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Phase-Lock Loop (PLL)
11.6.2 Reference Divider Registers
Address: $0042
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
RDV11 RDV10 RDV9 RDV8
Write:
Reset: 0
0
0
0
1
1
1
1
= Unimplemented
Figure 11-5. Reference Divider Register High (RDVH)
Address: $0043
Bit 7
6
5
4
3
2
1
Read:
RDV7
Write:
RDV6
RDV5
RDV4
RDV3
RDV2
RDV1
Reset: 1
1
1
1
1
1
1
Figure 11-6. Reference Divider Register Low (RDVL)
Bit 0
RDV0
1
Read: Anytime
Write: Anytime
The count in the reference divider (RDV) 12-bit register divides the
crystal oscillator clock input.
In the reset condition, both LDV and RDV are set to the maximum count
which produces an internal frequency at the phase detector of 8.2 kHz
and a final output frequency of 16.8 MHz with a 16.8 MHz input clock.
MC68HC812A4 — Rev. 3.0
172
Phase-Lock Loop (PLL)
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