MC68HC812A4 Datasheet, PDF (295/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Analog-to-Digital Converter (ATD)
Registers and Reset Initialization
PRS[4:0] — Prescaler Select Bits
The prescaler divides the P-clock by the binary value written to
PRS[4:0] plus one. To assure symmetry of the prescaler output, an
additional divide-by-two circuit generates the ATD module clock.
Clearing PRS[4:0] means the P-clock is divided only by the
divide-by-two circuit.
The reset state of PRS[4:0] is 00001, giving a total P-clock divisor of
four, which is appropriate for nominal operation at 2 MHz. Table 16-3
shows the appropriate range of system clock frequencies for each P
clock divisor.
Table 16-3. Clock Prescaler Values
PRS[4:0]
P-Clock
Divisor
Max P-Clock⁽¹⁾
Min P-Clock⁽²⁾
00000
2
4 MHz
1 MHz
00001
4
8 MHz
2 MHz
00010
6
8 MHz
3 MHz
00011
8
8 MHz
4 MHz
00100
10
8 MHz
5 MHz
00101
12
8 MHz
6 MHz
00110
14
8 MHz
7 MHz
00111
16
8 MHz
8 MHz
01xxx
1xxxx
Do not use
1. Maximum conversion frequency is 2 MHz. Maximum P-clock divisor value becomes max-
imum conversion rate that can be used on this ATD module.
2. Minimum conversion frequency is 500 kHz. Minimum P-clock divisor value becomes min-
imum conversion rate that this ATD can perform.
Advance Information
MOTOROLA
Analog-to-Digital Converter (ATD)
MC68HC812A4 — Rev. 3.0
295