MC68HC812A4 Datasheet, PDF (49/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Register Map
Addr.
$003F
$0040
$0041
$0042
$0043
$0044
Register Name
Chip-Select Stretch ^Read:
Register 1 (CSSTR1) Write:
See page 139. _Reset:
Loop Divider Register ^Read:
High (LDVH) Write:
See page 171. _Reset:
Loop Divider Register ^Read:
Low (LDVL) Write:
See page 171. _Reset:
Reference Divider ^Read:
Register High (RDVH) Write:
See page 172. _Reset:
Reference Divider ^Read:
Register Low (RDVL) Write:
See page 172. _Reset:
Reserved
Bit 7
STR3A
0
0
0
LDV7
1
0
0
RDV7
1
R
6
STR3B
0
0
0
LDV6
1
0
0
RDV6
1
R
5
STR2A
1
0
0
LDV5
1
0
0
RDV5
1
R
4
STR2B
1
0
0
LDV4
1
0
0
RDV4
1
R
3
STR1A
1
LDV11
1
LDV3
1
RDV11
1
RDV3
1
R
2
STR1B
1
LDV10
1
LDV2
1
RDV10
1
RDV2
1
R
1
STR0A
1
LDV9
1
LDV1
1
RDV9
1
RDV1
1
R
Bit 0
STR0B
1
LDV8
1
LDV0
1
RDV8
1
RDV0
1
R
$0045
Reserved
R
R
R
R
R
R
R
R
$0046
Reserved
R
R
R
R
R
R
R
R
Clock Control Register ^Read:
$0047
(CLKCTL) Write:
See page 173. _Reset:
$0048
Reserved
↓
↓
$005F
Reserved
LCKF
0
R
R
PLLON
0
R
R
PLLS
0
R
R
BCSC
0
R
R
BCSB
0
R
R
BCSA
0
R
R
MCSB
0
R
MCSA
0
R
R
R
ATD Control Register 0 ^Read: ₀
0
0
$0060
(ATDCTL0) Write:
See page 291. _{Reset: 0}
0
0
ATD Control Register 1 ^{Read: 0}
0
0
$0061
(ATDCTL1) Write:
See page 291. _{Reset: 0}
0
0
= Unimplemented
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 6 of 15)
Advance Information
MOTOROLA
Register Block
MC68HC812A4 — Rev. 3.0
49