MC68HC812A4 Datasheet, PDF (144/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Key Wakeups
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on remapping the register
block, refer to Section 5. Operating Modes and Resource Mapping.
9.3 Key Wakeup Registers
This section provides a summary of the key wakeup registers.
9.3.1 Port D Data Register
Address: $0005
Bit 7
6
5
4
3
2
Read:
PD7
PD6
PD5
PD4
PD3
PD2
Write:
Reset: 0
0
0
0
0
0
Alternate pin function: KWD7 KWD6 KWD5 KWD4 KWD3 KWD2
Figure 9-1. Port D Data Register (PORTD)
1
PD1
0
KWD1
Bit 0
PD0
0
KWD0
This register is not in the map in wide expanded modes or in special
expanded narrow mode with MODE register bit EMD set.
An interrupt is generated when a bit in the KWIFD register and its
corresponding KWIED bit are both set. These bits correspond to the pins
of port D. All eight bits/pins share the same interrupt vector and can
wake the CPU when it is in stop or wait mode. Key wakeups can be used
with the pins configured as inputs or outputs.
Key wakeup port D shares a vector and control bit with IRQ. IRQEN must
be set for key wakeup interrupts to signal the CPU.
MC68HC812A4 — Rev. 3.0
144
Key Wakeups
Advance Information
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