MC68HC812A4 Datasheet, PDF (56/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Addr.
$00C2
Register Name
SCI 0 Control
Register 1 (SC0CR1)
See page 250.
$00C3
SCI 0 Control
Register 2 (SC0CR2)
See page 252.
$00C4
SCI 0 Status
Register 1 (SC0SR1)
See page 254.
$00C5
SCI 0 Status
Register 2 (SC0SR2)
See page 256.
$00C6
SCI 0 Data Register
High (SC0DRH)
See page 257.
$00C7
SCI 0 Data Register
Low (SC0DRL)
See page 257.
$00C8
SCI 1 Baud Rate
Register High
(SC1BDH)
See page 249.
SCI 1 Baud Rate
$00C9 Register Low (SC1BDL)
See page 249.
SCI 1 Control Register
$00CA
1 (SC1CR1)
See page 250.
SCI 1 Control Register
$00CB
2 (SC1CR2)
See page 252.
SCI 1 Status Register 1
$00CC
(SC1SR1)
See page 254.
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
LOOPS
0
TIE
0
TDRE
1
0
0
R8
R7
T7
BTST
0
SBR7
0
LOOPS
0
TIE
0
TDRE
1
6
WOMS
0
TCIE
0
TC
5
RSRC
0
RIE
0
RDRF
1
0
0
0
0
0
0
T8
R6
R5
T6
T5
BSPL BRLD
0
0
SBR6
0
WOMS
0
TCIE
0
TC
SBR5
0
RSRC
0
RIE
0
RDRF
1
0
= Unimplemented
4
3
2
M
WAKE
ILT
0
0
0
ILIE
TE
RE
0
0
0
IDLE
OR
NF
1
Bit 0
PE
PT
0
0
RWU
SBK
0
0
FE
PF
0
0
0
0
0
0
0
0
0
RAF
0
0
0
0
0
0
0
0
0
0
Unaffected by reset
R4
R3
R2
T4
T3
T2
Unaffected by reset
SBR12 SBR11 SBR10
0
0
0
SBR4
0
M
0
ILIE
0
IDLE
SBR3
0
WAKE
0
TE
0
OR
SBR2
1
ILT
0
RE
0
NF
R1
T1
SBR9
0
SBR1
0
PE
0
RWU
0
FE
R0
T0
SBR8
0
SBR0
0
PT
0
SBK
0
PF
0
0
0
0
0
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 13 of 15)
MC68HC812A4 — Rev. 3.0
56
Register Block
Advance Information
MOTOROLA