MC68HC812A4 Datasheet, PDF (76/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Resets and Interrupts
4.7.1 Operating Mode and Memory Map
The states of the BGND, MODA, and MODB pins during reset determine
the operating mode and default memory mapping. The SMODN, MODA,
and MODB bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
4.7.2 Clock and Watchdog Control Logic
Reset enables the COP watchdog with the CR2–CR0 bits set for the
longest timeout period. The clock monitor is disabled. The RTIF flag is
cleared and automatic hardware interrupts are masked. The rate control
bits are cleared, and must be initialized before the RTI system is used.
The DLY control bit is set to specify an oscillator startup delay upon
recovery from stop mode.
4.7.3 Interrupts
Reset initializes the HPRIO register with the value $F2, causing the IRQ
pin to have the highest I bit interrupt priority. The IRQ pin is configured
for level-sensitive operation (for wired-OR systems). However, the I and
X bits in the CCR are set, masking IRQ and XIRQ interrupt requests.
4.7.4 Parallel I/O
If the MCU comes out of reset in an expanded mode, port A and port B
are the address bus. Port C and port D are the data bus. In narrow mode,
port C alone is the data bus. Port E pins are normally used to control the
external bus. The PEAR register affects port E pin operation.
If the MCU comes out of reset in a single-chip mode, all ports are
configured as general-purpose, high-impedance inputs except in normal
narrow expanded mode (NNE). In NNE, PE3 is configured as an output
driven high.
In expanded modes, PF5 is an active chip-select.
MC68HC812A4 — Rev. 3.0
76
Resets and Interrupts
Advance Information
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