MC68HC812A4 Datasheet, PDF (24/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

List of Figures
Figure
Title
Page
15-6 Transmission Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . .270
15-7 Slave SS When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .270
15-8 Single-Wire Operation (SPC0 = 1) . . . . . . . . . . . . . . . . . . . . .272
15-9 SPI Control Register 1 (SP0CR1). . . . . . . . . . . . . . . . . . . . . .273
15-10 SPI Control Register 2 (SP0CR2). . . . . . . . . . . . . . . . . . . . . .275
15-11 SPI Baud Rate Register (SP0BR) . . . . . . . . . . . . . . . . . . . . .276
15-12 SPI Status Register (SP0SR) . . . . . . . . . . . . . . . . . . . . . . . . .277
15-13 SPI Data Register (SP0DR) . . . . . . . . . . . . . . . . . . . . . . . . . .278
16-1 ATD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
16-2 ATD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .288
16-3 ATD Control Register 0 (ATDCTL0) . . . . . . . . . . . . . . . . . . . .291
16-4 ATD Control Register 1 (ATDCTL1) . . . . . . . . . . . . . . . . . . . .291
16-5 ATD Control Register 2 (ATDCTL2) . . . . . . . . . . . . . . . . . . . .292
16-6 ATD Control Register 3 (ATDCTL3) . . . . . . . . . . . . . . . . . . . .293
16-7 ATD Control Register 4 (ATDCTL4) . . . . . . . . . . . . . . . . . . . .294
16-8 ATD Control Register 5 (ATDCTL5) . . . . . . . . . . . . . . . . . . . .296
16-9 ATD Status Register 1 (ATDSTAT1) . . . . . . . . . . . . . . . . . . .298
16-10 ATD Status Register 2 (ATDSTAT2) . . . . . . . . . . . . . . . . . . .298
16-11 ATD Test Register 1 (ATDTEST1) . . . . . . . . . . . . . . . . . . . . .299
16-12 ATD Test Register 2 (ATDTEST2) . . . . . . . . . . . . . . . . . . . . .299
16-13 ATD Result Registers (ADR0H–ADR7H) . . . . . . . . . . . . . . . .300
16-14 Port AD Data Input Register (PORTAD). . . . . . . . . . . . . . . . .302
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
BDM Host-to-Target Serial Bit Timing . . . . . . . . . . . . . . . . . .309
BDM Target-to-Host Serial Bit Timing (Logic 1) . . . . . . . . . . .310
BDM Target-to-Host Serial Bit Timing (Logic 0) . . . . . . . . . . .310
BDM Instruction Register (INSTRUCTION) . . . . . . . . . . . . . .314
BDM Instruction Register (INSTRUCTION) . . . . . . . . . . . . . .315
BDM Status Register (STATUS). . . . . . . . . . . . . . . . . . . . . . .317
BDM Shift Register (SHIFTER) . . . . . . . . . . . . . . . . . . . . . . .318
BDM Address Register (ADDRESS) . . . . . . . . . . . . . . . . . . .318
BDM CCR Holding Register (CCRSAV) . . . . . . . . . . . . . . . . .319
MC68HC812A4 — Rev. 3.0
24
List of Figures
Advance Information
MOTOROLA