MC68HC812A4 Datasheet, PDF (219/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Multiple Serial Interface (MSI)
General-Purpose I/O Ports
13.7.1 Port S Data Register
Address: $00D6
Bit 7
6
5
4
3
2
1
Read:
PS7
PS6
PS5
PS4
PS3
PS2
PS1
Write:
Reset:
Unaffected by reset
Pin function: SS
SCK MOSI MISO TXD1 RXD1 TXD0
Figure 13-3. Port S Data Register (PORTS)
Read: Anytime
Write: Anytime
Bit 0
PS0
RXD0
PS7–PS4 — Port S Data Bits 7–4
Port S shares PS7–PS4 with SPI0.
SS is the SPI0 slave-select terminal.
SCK is the SPI0 serial clock terminal.
MOSI is the SPI0 master out, slave in terminal.
MISO is the SPI0 master in, slave out terminal.
PS3–PS0 — Port S Data Bits 3–0
Port S shares PS3–0 with SCI1 and SCI0.
TXD1 is the SCI1 transmit terminal.
RXD1 is the SCI1 receive terminal.
TXD0 is the SCI0 transmit terminal.
RXD0 is the SCI0 receive terminal.
NOTE:
Reading a port S bit when its data direction bit is clear returns the level
of the voltage on the pin. Reading a port S bit when its data direction bit
is set returns the level of the voltage of the pin driver input.
A write to a port S bit is stored in an internal latch. The latch drives the
pin only when the corresponding data direction bit is set.
Writes do not change the pin state when the pin is configured for SCI
output.
Advance Information
MOTOROLA
Multiple Serial Interface (MSI)
MC68HC812A4 — Rev. 3.0
219