MC68HC812A4 Datasheet, PDF (274/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Peripheral Interface (SPI)
MSTR — Master Mode Bit
MSTR selects master mode operation or slave mode operation.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
CPOL determines the logic state of the serial clock pin between
transmissions. See Figure 15-4 and Figure 15-6.
1 = Active-high SCK
0 = Active-low SCK
CPHA — Clock Phase Bit
CPHA determines whether transmission begins on the falling edge of
the SS pin or on the first edge of the serial clock. See Figure 15-4 and
Figure 15-6.
1 = Transmission at first SCK edge
0 = Transmission at falling SS edge
SSOE — Slave Select Output Enable Bit
SSOE enables the output function of master SS pin when the DDRS7
bit is also set.
1 = SS output enabled
0 = SS output disabled
LSBF — LSB First Bit
LSBF enables least-significant-bit-first transmissions. It does not
affect the position of data in the SPI data register; reads and writes of
the SPI data register always have the MSB in bit 7.
1 = Least-significant-bit-first transmission
0 = Most-significant-bit-first transmission
MC68HC812A4 — Rev. 3.0
274
Serial Peripheral Interface (SPI)
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