MC68HC812A4 Datasheet, PDF (71/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Resets and Interrupts
Maskable Interrupts
4.4 Maskable Interrupts
Maskable interrupt sources include on-chip peripheral systems and
external interrupt service requests. Interrupts from these sources are
recognized when the global interrupt mask bit (I) in the CCR is cleared.
The default state of the I bit out of reset is 1, but it can be written at any
time.
Interrupt sources are prioritized by default but any one maskable
interrupt source may be assigned the highest priority by means of the
HPRIO register. The relative priorities of the other sources remain the
same.
An interrupt that is assigned highest priority is still subject to global
masking by the I bit in the CCR or by any associated local bits. Interrupt
vectors are not affected by priority assignment. HPRIO can only be
written while the I bit is set (interrupts inhibited). Table 4-1 lists interrupt
sources and vectors in default order of priority.
Table 4-1. Interrupt Vector Map
Vector
Address
Exception Source
$FFFE, $FFFF Power-on reset
$FFFC, $FFFD COP clock monitor reset
$FFFA, $FFFB COP reset
$FFF8, $FFF9 Unimplemented instruction trap
$FFF6, $FFF7 SWI instruction
$FFF4, $FFF5 XIRQ pin
$FFF2, $FFF3 IRQ pin or key wakeup D
$FFF0, $FFF1 Real-time interrupt
$FFEE, $FFEF Timer channel 0
$FFEC, $FFED Timer channel 1
$FFEA, $FFEB Timer channel 2
$FFE8, $FFE9 Timer channel 3
$FFE6, $FFE7 Timer channel 4
Flag
—
—
—
—
—
—
—
RTIF
C0F
C1F
C2F
C3F
C4F
Local
Enable
None
CME, FCME
COP rate selected
None
None
None
IRQEN, KWIED7–0
RTIE
C0I
C1I
C2I
C3I
C4I
CCR HPRIO Value
Mask to Elevate
None
—
None
—
None
—
None
—
None
—
X bit
—
I bit
$F2
I bit
$F0
I bit
$EE
I bit
$EC
I bit
$EA
I bit
$E8
I bit
$E6
Advance Information
MOTOROLA
Resets and Interrupts
MC68HC812A4 — Rev. 3.0
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