MC68HC812A4 Datasheet, PDF (57/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Register Map
Addr.
Register Name
Bit 7
SCI 1 Status Register 2 ^{Read: 0}
$00CD
(SC1SR2) Write:
See page 256. _{Reset: 0}
SCI 1 Data Register ^{Read: R8}
$00CE
High (SC1DRH) Write:
See page 257. _Reset:
SCI 1 Data Register ^{Read: R7}
$00CF
Low (SC1DRL) Write: T7
See page 257. _Reset:
SPI 0 Control Register ^Read: _SPIE
$00D0
1 (SP0CR1) Write:
See page 273. _{Reset: 0}
SPI 0 Control Register ^{Read: 0}
$00D1
2 (SP0CR2) Write:
See page 275. _{Reset: 0}
SPI Baud Rate Register ^{Read: 0}
$00D2
(SP0BR) Write:
See page 276. _{Reset: 0}
$00D3
SPI Status Register ^{Read: SPIF}
(SP0SR) Write:
See page 277. _{Reset: 0}
$00D4
Reserved
R
6
5
4
3
2
0
0
0
0
0
0
T8
R6
T6
SPE
0
0
0
0
0
WCOL
0
0
R5
T5
SWOM
0
0
0
0
0
0
0
0
0
0
Unaffected by reset
R4
R3
T4
T3
Unaffected by reset
MSTR CPOL
0
0
0
PUPS
0
1
0
0
0
0
MODF
0
0
0
R2
T2
CPHA
1
RDS
0
SPR2
0
0
0
0
0
0
0
R
R
R
R
R
1
0
0
0
R1
T1
SSOE
0
0
0
SPR1
0
0
0
R
Bit 0
RAF
0
0
R0
T0
LSBF
0
SPC0
0
SPR0
0
0
0
R
$00D5
$00D6
$00D7
SPI Data Register ^Read: _{Bit 7}
Bit 6
Bit 5
(SP0DR) Write:
See page 278. _Reset:
Port S Data Register ^Read: _PS7
PS6
PS5
(PORTS) Write:
See page 219. _Reset:
Port S Data Direction
Register (DDRS)
See page 220.
Read:
Write:
Reset:
DDRS7
0
DDRS6
0
DDRS5
0
= Unimplemented
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unaffected by reset
PS4
PS3
PS2
PS1
PS0
Unaffected by reset
DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
0
0
0
0
0
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 14 of 15)
Advance Information
MOTOROLA
Register Block
MC68HC812A4 — Rev. 3.0
57