MC68HC812A4 Datasheet, PDF (293/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Analog-to-Digital Converter (ATD)
Registers and Reset Initialization
ASCIE — ATD Sequence Complete Interrupt Enable Bit
ASCIE enables interrupt requests generated by the ATD sequence
complete interrupt flag, ASCIF.
1 = ASCIF interrupt requests enabled
0 = ASCIF interrupt requests disabled
ASCIF — ATD Sequence Complete Interrupt Flag
ASCIF is set when a conversion sequence is finished. If the ATD
sequence complete interrupt enable bit, ASCIE, is also set, ASCIF
generates an interrupt request.
1 = Conversion sequence complete
0 = Conversion sequence not complete
NOTE:
The ASCIF flag is set only when a conversion sequence is completed
and ASCIE = 1 or interrupts on the analog-to-digital converter (ATD)
module are enabled.
16.7.4 ADT Control Register 3
Address: $0063
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
FRZ1 FRZ0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-6. ATD Control Register 3 (ATDCTL3)
FRZ1 and FRZ0 — Freeze Bits
The FRZ bits suspend ATD operation for background debugging.
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint is encountered. These two bits
determine how the ATD responds when background debug mode
becomes active. See Table 16-1.
Advance Information
MOTOROLA
Analog-to-Digital Converter (ATD)
MC68HC812A4 — Rev. 3.0
293