MC68HC812A4 Datasheet, PDF (171/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Phase-Lock Loop (PLL)
Registers and Reset Initialization
A passive external loop filter must be placed on the control line (XFC
pad). The filter is a second-order, low-pass filter to eliminate the VCO
input ripple.
11.6 Registers and Reset Initialization
This section describes the registers and reset initialization.
11.6.1 Loop Divider Registers
Address: $0040
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
LDV11 LDV10 LDV9 LDV8
Write:
Reset: 0
0
0
0
1
1
1
1
= Unimplemented
Figure 11-3. Loop Divider Register High (LDVH)
Address: $0041
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LDV7 LDV6 LDV5 LDV4 LDV3 LDV2 LDV1 LDV0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 11-4. Loop Divider Register Low (LDVL)
Read: Anytime
Write: Anytime
If the PLL is on, the count in the loop divider (LDV) 12-bit register
effectively multiplies up from the PLL base frequency.
CAUTION: Do not exceed the maximum rated operating frequency for the CPU.
Advance Information
MOTOROLA
Phase-Lock Loop (PLL)
MC68HC812A4 — Rev. 3.0
171