MC68HC812A4 Datasheet, PDF (54/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Addr.
$0096
$0097
$0098
$0099
$009A
$009B
$009C
$009D
$009E
$009F
$00A0
Register Name
Timer Channel 3 ^Read:
Register High (TC3H) Write:
See page 197. _Reset:
Timer Channel 3 ^Read:
Register Low (TC3L) Write:
See page 197. _Reset:
Timer Channel 4 ^Read:
Register High (TC4H) Write:
See page 197. _Reset:
Timer Channel 4 ^Read:
Register Low (TC4L) Write:
See page 197. _Reset:
Timer Channel 5 ^Read:
Register High (TC5H) Write:
See page 197. _Reset:
Timer Channel 5 ^Read:
Register Low (TC5L) Write:
See page 197. _Reset:
Timer Channel 6 ^Read:
Register High (TC6H) Write:
See page 197. _Reset:
Timer Channel 6 ^Read:
Register Low (TC6L) Write:
See page 197. _Reset:
Timer Channel 7 ^Read:
Register High (TC7H) Write:
See page 197. _Reset:
Timer Channel 7 ^Read:
Register Low (TC7L) Write:
See page 197. _Reset:
Pulse Accumulator
Control Register
(PACTL)
See page 198.
Read:
Write:
Reset:
Bit 7
Bit 15
0
Bit 7
0
Bit 15
0
Bit 7
0
Bit 15
0
Bit 7
0
Bit 15
0
Bit 7
0
Bit 15
0
Bit 7
0
0
0
6
Bit 14
0
Bit 6
0
Bit 14
0
Bit 6
0
Bit 14
0
Bit 6
0
Bit 14
0
Bit 6
0
Bit 14
0
Bit 6
0
PAEN
5
Bit 13
0
Bit 5
0
Bit 13
0
Bit 5
0
Bit 13
0
Bit 5
0
Bit 13
0
Bit 5
0
Bit 13
0
Bit 5
0
PAMOD
0
0
= Unimplemented
4
Bit 12
0
Bit 4
0
Bit 12
0
Bit 4
0
Bit 12
0
Bit 4
0
Bit 12
0
Bit 4
0
Bit 12
0
Bit 4
0
PEDGE
3
Bit 11
0
Bit 3
0
Bit 11
0
Bit 3
0
Bit 11
0
Bit 3
0
Bit 11
0
Bit 3
0
Bit 11
0
Bit 3
0
CLK1
2
Bit 10
0
Bit 2
0
Bit 10
0
Bit 2
0
Bit 10
0
Bit 2
0
Bit 10
0
Bit 2
0
Bit 10
0
Bit 2
0
CLK0
0
0
0
R = Reserved
1
Bit 0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
Bit 9
Bit 8
0
0
Bit 1
Bit 0
0
0
PAOVI
PAI
0
0
U = Unaffected
Figure 2-1. Register Map (Sheet 11 of 15)
MC68HC812A4 — Rev. 3.0
54
Register Block
Advance Information
MOTOROLA