MC68HC812A4 Datasheet, PDF (100/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Bus Control and Input/Output (I/O)
6.4.7 Port D Data Register
Address: $0005
Bit 7
6
5
4
3
2
Read:
PD7
PD6
PD5
PD4
PD3
PD2
Write:
Reset: 0
0
0
0
0
0
Expanded wide and peripheral: DATA7 DATA6 DATA5 DATA4 DATA3 DATA2
Alternate pin function: KWD7 KWD6 KWD5 KWD4 KWD3 KWD2
Figure 6-7. Port D Data Register (PORTD)
1
PD1
0
DATA1
KWD1
Bit 0
PD0
0
DATA0
KWD0
Read: Anytime, if register is in the map
Write: Anytime, if register is in the map
Bits PD7–PD0 correspond to data lines DATA7–DATA0. When port D is
not used for external data, such as in single-chip mode, these pins can
be used as general-purpose I/O or key wakeup signals. DDRD
determines the primary direction of each port D pin.
In special expanded narrow mode, the external data bus is normally
limited to eight bits on port C, but the emulate port D bit (EMD) in the
MODE register can be set to allow port C and port D to be used together
to provide single-cycle visibility of internal 16-bit accesses for debugging
purposes. If the mode is special narrow expanded and EMD is set, port
D is configured for DATA7–DATA0 of visible internal accesses and
normal 16-bit external accesses are split into two adjacent 8-bit
accesses through port C. This allows connection of a single 8-bit
external program memory.
This register is not in the on-chip map in wide expanded and peripheral
modes. Also, in special narrow expanded mode, the function of this port
is determined by the EMD control bit. If EMD is set, this register is not in
the on-chip map and port D is used for DATA7–DATA0 of visible internal
accesses. If EMD is clear, this port serves as general-purpose I/O or key
wakeup signals.
MC68HC812A4 — Rev. 3.0
100
Bus Control and Input/Output (I/O)
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