MC68HC812A4 Datasheet, PDF (55/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Register Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Pulse Accumulator Flag ^{Read: Bit 0}
0
0
0
0
0
PAOVF PAIF
$00A1
Register (PAFLG) Write:
See page 200. _{Reset: 0}
0
0
0
0
0
0
0
Pulse Accumulator Read:
$00A2
Counter Register High
(PACNTH)
Write:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See page 201. ^{Reset: 0}
0
0
0
0
0
0
0
Pulse Accumulator Read:
$00A3
Counter Register Low
(PACNTL)
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See page 201. ^{Reset: 0}
0
0
0
0
0
0
0
$00A4
Reserved
R
R
R
R
R
R
R
R
↓
↓
$00AC
Reserved
R
R
R
R
R
R
R
R
Timer Test Register ^{Read: 0}
0
0
0
0
0
TCBYP PCBYP
$00AD
(TIMTST) Write:
See page 202. _{Reset: 0}
0
0
0
0
0
0
0
Timer Port Data ^Read: _PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
$00AE Register (PORTT) Write:
See page 206. _Reset:
Unaffected by reset
Timer Port Data Read:
$00AF
Direction Register _Write: ^{Bit 7}
(DDRT)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See page 207. ^{Reset: 0}
0
0
0
0
0
0
0
$00B0
Reserved
R
R
R
R
R
R
R
R
↓
↓
$00BF
Reserved
R
R
R
R
R
R
R
R
$00C0
SCI 0 Baud Rate
Register High
(SC0BDH)
See page 249.
Read:
Write:
Reset:
SCI 0 Baud Rate ^Read:
$00C1 Register Low (SC0BDL) Write:
See page 249. _Reset:
BTST
0
SBR7
0
BSPL BRLD
0
0
SBR6 SBR5
0
0
= Unimplemented
SBR12 SBR11 SBR10 SBR9 SBR8
0
0
0
0
0
SBR4 SBR3 SBR2 SBR1 SBR0
0
0
1
0
0
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 12 of 15)
Advance Information
MOTOROLA
Register Block
MC68HC812A4 — Rev. 3.0
55