MC68HC812A4 Datasheet, PDF (307/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

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Background Debug Mode (BDM)
Program information is fetched a few cycles before it is used by the CPU.
To monitor cycle-by-cycle CPU activity, it is necessary to externally
reconstruct what is happening in the instruction queue. Internally, the
MCU only needs to buffer the data from program fetches. For system
debug, it is necessary to keep the data and its associated address in the
reconstructed instruction queue. The raw signals required for
reconstruction of the queue are ADDR, DATA, R/W, ECLK, and status
signals IPIPE[1:0].
The instruction queue consists of two 16-bit queue stages and a holding
latch on the input of the first stage. To advance the queue means to
move the word in the first stage to the second stage and move the word
from either the holding latch or the data bus input buffer into the first
stage. To start even (or odd) instruction means to execute the opcode in
the high-order (or low-order) byte of the second stage of the instruction
queue.
17.4 Background Debug Mode (BDM)
Background debug mode (BDM) is used for:
• System development
• In-circuit testing
• Field testing
• Programming
BDM is implemented in on-chip hardware and provides a full set of
debug options.
Because BDM control logic does not reside in the CPU, BDM hardware
commands can be executed while the CPU is operating normally. The
control logic generally uses CPU dead cycles to execute these
commands, but can steal cycles from the CPU when necessary. Other
BDM commands are firmware based and require the CPU to be in active
background mode for execution. While BDM is active, the CPU executes
a firmware program located in a small on-chip ROM that is available in
the standard 64-Kbyte memory map only while BDM is active.
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MOTOROLA
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MC68HC812A4 — Rev. 3.0
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