MC68HC812A4 Datasheet, PDF (252/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Communications Interface Module (SCI)
ILT — Idle Line Type Bit
ILT determines when the receiver starts counting logic 1s as idle
character bits. The counting begins either after the start bit or after the
stop bit. If the count begins after the start bit, then a string of logic 1s
preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions.
1 = Idle character bit count begins after stop bit.
0 = Idle character bit count begins after start bit.
PE — Parity Enable Bit
PE enables the parity function. When enabled, the parity function
inserts a parity bit in the most significant bit position.
1 = Parity function enabled
0 = Parity function disabled
PT — Parity Type Bit
PT determines whether the SCI generates and checks for even parity
or odd parity. With even parity, an even number of 1s clears the parity
bit and an odd number of 1s sets the parity bit. With odd parity, an odd
number of 1s clears the parity bit and an even number of 1s sets the
parity bit.
1 = Odd parity
0 = Even parity
14.7.3 SCI Control Register 2
SCI0: $00C3
SCI1: $00CB
Bit 7
6
5
4
3
2
1
Bit 0
Read:
TIE
TCIE
RIE
ILIE
TE
RE
RWU SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 14-20. SCI Control Register 2 (SC0CR2 or SC1CR2)
Read: Anytime
Write: Anytime
MC68HC812A4 — Rev. 3.0
252
Serial Communications Interface Module (SCI)
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