MC68HC812A4 Datasheet, PDF (309/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Development Support
Background Debug Mode (BDM)
E CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
SYNCHRONIZATION
UNCERTAINTY
PERCEIVED START
OF BIT TIME
10 CYCLES
TARGET SENSES BIT LEVEL
EARLIEST START
OF NEXT BIT
Figure 17-1. BDM Host-to-Target Serial Bit Timing
Figure 17-2 shows the host receiving a logic 1 from the target
MC68HC812A4 MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The
host holds the BKGD pin low long enough for the target to recognize it
(at least two target E cycles). The host must release the low drive before
the target MCU drives a brief active-high speed-up pulse seven cycles
after the perceived start of the bit time. The host should sample the bit
level about 10 cycles after it started the bit time.
Figure 17-3 shows the host receiving a logic 0 from the target
MC68HC812A4 MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the start of the bit time as perceived by the target MCU. The
host initiates the bit time but the target MC68HC812A4 finishes it. Since
the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 E-clock cycles, then briefly drives it high to speed up the rising
edge. The host samples the bit level about 10 cycles after starting the bit
time.
Advance Information
MOTOROLA
Development Support
MC68HC812A4 — Rev. 3.0
309