MC68HC812A4 Datasheet, PDF (173/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

11.6.3 Clock Control Register
Phase-Lock Loop (PLL)
Registers and Reset Initialization
Address: $0047
Bit 7
6
5
4
3
2
1
Read: LCKF
Write:
PLLON
PLLS
BCSC
BCSB
BCSA MCSB
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 11-7. Clock Control Register (CLKCTL)
Bit 0
MCSA
0
Read: Anytime
Write: Anytime
LCKF — Lock Flag
This read-only flag is set when the PLL frequency is at least half the
target frequency and no more than twice the target frequency.
1 = PLL locked
0 = PLL not locked
PLLON — PLL On Bit
Setting PLLON turns on the PLL.
1 = PLL on
0 = PLL off
PLLS — PLL Select Bit (PLL output or crystal input frequency)
PLLS selects the PLL after the LCKF flag is set.
1 = PLL selected
0 = Crystal input selected
BCS[C:B:A] — Base Clock Select Bits
These bits determine the frequency of SYSCLK. SYSCLK is the
source clock for the MCU, including the CPU and buses. See
Table 11-2. SYSCLK and is twice the bus rate. MUXCLK is either the
PLL output or the crystal input frequency as selected by the PLLS bit.
Advance Information
MOTOROLA
Phase-Lock Loop (PLL)
MC68HC812A4 — Rev. 3.0
173