MC68HC812A4 Datasheet, PDF (204/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Standard Timer Module
12.8 Background Debug Mode
If the TSBCK bit is clear, background debug mode has no effect on the
timer. If TSBCK is set, background debug mode disables the timer.
NOTE: Setting TSBCK does not stop the pulse accumulator when it is in event
counter mode.
12.9 Low-Power Options
This section describes the three low-power modes:
• Run mode
• Wait mode
• Stop mode
12.9.1 Run Mode
Clearing the timer enable bit (TEN) or the pulse accumulator enable bit
(PAEN) reduces power consumption in run mode. TEN is in the timer
system control register (TSCR). PAEN is in the pulse accumulator
control register (PACTL). Timer and pulse accumulator registers are still
accessible, but clocks to the core of the timer are disabled.
12.9.2 Wait Mode
Timer and pulse accumulator operation in wait mode depend on the
state of the TSWAI bit in the timer system control register TSCR).
• If TSWAI is clear, the timer and pulse accumulator operate
normally when the CPU is in wait mode.
• If TSWAI is set, timer and pulse accumulator clock generation
ceases and the TIM module enters a power-conservation state
when the CPU is in wait mode. In this condition, timer and pulse
accumulator registers are not accessible. Setting TSWAI does not
affect the state of the timer enable bit, TEN, or the pulse
accumulator enable bit, PAEN.
MC68HC812A4 — Rev. 3.0
204
Standard Timer Module
Advance Information
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