MC68HC812A4 Datasheet, PDF (270/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Peripheral Interface (SPI)
When CPHA = 1, the master begins driving its MOSI pin and the slave
begins driving its MISO pin on the first serial clock edge. The SS pin can
remain low between transmissions. This format may be preferable in
systems having only one slave driving the master MISO line.
NOTE: The slave SCK pin must be in the proper idle state before the slave is
enabled.
t_L
BEGIN
TRANSFER
SCK CYCLES
1
2
3
4
5
6
7
SCK
CPOL = 0
SCK
CPOL = 1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS
TO SLAVE
CAPTURE STROBE
MSB FIRST (LSBF = 0)
LSB FIRST (LSBF = 1)
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
MINIMUM t_L, t_T, and t_I = 1/2 SCK CYCLE
Figure 15-6. Transmission Format 1 (CPHA = 1)
t_T
END
TRANSFER
8
t_I
LSB
MSB
MISO/MOSI
MASTER SS
SLAVE SS
CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 15-7. Slave SS When CPHA = 1
MC68HC812A4 — Rev. 3.0
270
Serial Peripheral Interface (SPI)
Advance Information
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