MC68HC812A4 Datasheet, PDF (32/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

General Description
1.5 Block Diagram
BKGD/TAGHI
RESET
EXTAL
XTAL
XFC
V_DDPLL
V_SSPLL
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
1-KBYTE SRAM
V_RH
V_RL
V_DDA
V_SSA
4-KBYTE EEPROM
CPU12
SINGLE-WIRE
BACKGROUND
DEBUG MODULE
PERIODIC INTERRUPT
COP WATCHDOG
PLL CLOCK
CONTROL
CLOCK MONITOR
INTERRUPT BLOCK
ARST
IPIPE1/MODB
IPIPE0/MODA
ECLK
LSTRB/TAGLO
R/W
IRQ/V_PP
XIRQ
KWJ7
KWJ6
KWJ5
KWJ4
KWJ3
KWJ2
KWJ1
KWJ0
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
LIM
LITE INTEGRATION MODULE
CSP1
CSP0
CSD
CS3
CS2
CS1
CS0
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
DATA7/KWD7
DATA6/KWD6
DATA5/KWD5
DATA4/KWD4
DATA3/KWD3
DATA2/KWD2
DATA1/KWD1
DATA0/KWD0
NON-MULTIPLEXED
ADDRESS/DATA BUS
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
V_STBY/AN7
AN6
A/D
AN5
CONVERTER AN4
AN3
AN2
AN1
AN0
IOC7/PAI
IOC6
IOC5
TIM OC7 ^IOC4
IOC3
IOC2
IOC1
IOC0
SS
SPI0
SCK
SDO/MOSI
MSI
SDI/MISO
SCI1
TXD1
RXD1
SCI0
TXD0
RXD0
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PG5
PG4
PG3
PG2
PG1
PG0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Figure 1-1. Block Diagram
MC68HC812A4 — Rev. 3.0
32
General Description
V_RH
V_RL
V_DDA
V_SSA
PAD7V_STBY
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
V_DDEXT x3
V_SSEXT x3
V_DD x1
V_SSI x1
Advance Information
MOTOROLA