MC68HC812A4 Datasheet, PDF (78/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Resets and Interrupts
Table 4-2. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
Stacked Values
RTN_H : RTN_L
Y_H : Y_L
X_H : X_L
B:A
CCR
After stacking the CCR, the CPU:
• Sets the I bit to prevent other interrupts from disrupting the
interrupt service routine
• Sets the X bit if an XIRQ interrupt request is pending
• Fetches the interrupt vector for the highest-priority request that
was pending at the beginning of the interrupt sequence
• Begins execution of the interrupt service routine at the location
pointed to by the vector
If no other interrupt request is pending at the end of the interrupt service
routine, an RTI instruction recovers the stacked values. Program
execution resumes program at the return address.
If another interrupt request is pending at the end of an interrupt service
routine, the RTI instruction recovers the stacked values. However, the
CPU then:
• Adjusts the stack pointer to point again at the stacked CCR
location, SP – 9
• Fetches the vector of the pending interrupt
• Begins execution of the interrupt service routine at the location
pointed to by the vector
MC68HC812A4 — Rev. 3.0
78
Resets and Interrupts
Advance Information
MOTOROLA