MC68HC812A4 Datasheet, PDF (112/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

EEPROM
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes), or bulk erase, all using the internal charge pump. Bulk
erasure of odd and even rows is also possible in test modes; the erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
program/erase voltage. Programming voltage is derived from the
internal V_DD supply with an internal charge pump. The EEPROM has a
minimum program/erase life of 10,000 cycles over the complete
operating temperature range.
7.3 EEPROM Programmer’s Model
The EEPROM module consists of two separately addressable sections.
The first is a 4-byte memory mapped control register block used for
control, testing and configuration of the EEPROM array. The second
section is the EEPROM array itself.
At reset, the 4-byte register section starts at address $00F0 and the
EEPROM array is located from addresses $1000 to $1FFF
(see Figure 7-1). For information on remapping the register block and
EEPROM address space, refer to Section 5. Operating Modes and
Resource Mapping.
Read/write access to the memory array section can be enabled or
disabled by the EEON control bit in the INITEE register. This feature
allows the access of memory mapped resources that have lower priority
than the EEPROM memory array. EEPROM control registers can be
accessed and EEPROM locations may be programmed or erased
regardless of the state of EEON.
Using the normal EEPROG control, it is possible to continue
program/erase operations during wait. For lowest power consumption
during wait, stop program/erase by turning off EEPGM.
MC68HC812A4 — Rev. 3.0
112
EEPROM
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