MC68HC812A4 Datasheet, PDF (268/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Peripheral Interface (SPI)
15.6.2 Slave Mode
The SPI operates in slave mode when MSTR is clear. In slave mode, the
SCK pin is the input for the serial clock from the master.
NOTE:
Before a transmission occurs, the SS pin of the slave SPI must be at
logic 0. The slave SS pin must remain low until the transmission is
complete.
A transmission begins when initiated by a master SPI. The byte from the
master SPI begins shifting in on the slave MOSI pin under the control of
the master serial clock.
As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin
to the master shift register. On the eighth serial clock cycle, the
transmission ends and sets the SPI flag, SPIF. At the same time that
SPIF becomes set, the byte from the master transfers to the SPI data
register. The byte remains in a read buffer until replaced by the next byte
from the master.
15.6.3 Baud Rate Generation
A clock divider in the SPI produces eight divided P-clock signals. The
P-clock divisors are 2, 4, 8, 16, 32, 64, 128, and 256. The SPR[2:1:0] bits
select one of the divided P-clock signals to control the rate of the shift
register. Through the SCK pin, the selected clock signal also controls the
rate of the shift register of the slave SPI or other slave peripheral.
The clock divider is active only in master mode and only when a
transmission is taking place. Otherwise, the divider is disabled to save
power.
15.6.4 Clock Phase and Polarity
The clock phase and clock polarity bits, CPHA and CPOL, can select
any of four combinations of serial clock phase and polarity. The CPHA
bit determines whether a falling SS edge or the first SCK edge begins
the transmission. The CPOL bit determines whether SCK is active-high
or active-low.
MC68HC812A4 — Rev. 3.0
268
Serial Peripheral Interface (SPI)
Advance Information
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