MC68HC812A4 Datasheet, PDF (165/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Clock Module
Registers and Reset Initialization
DISR — Disable Reset Bit
Write: Never in normal modes; anytime in special modes
DISR disables clock monitor resets and COP resets.
1 = Clock monitor and COP resets disabled
0 = Normal operation
CR2, CR1, and CR0 — COP Watchdog Timer Rate Select Bits
Write: Once in normal modes, anytime in special modes
The COP system is driven by a constant frequency of M/2¹³. These
bits specify an additional division factor to arrive at the COP timeout
rate. (The clock used for this module is the M-clock.)
Table 10-3. COP Watchdog Rates
CR[2:1:0] M-Clock Divisor
000
OFF
001
2¹³
010
2¹⁵
011
2¹⁷
100
2¹⁹
101
2²¹
110
2²²
111
2²³
COP Timeout Period
0/+2.048 ms 0/+1.024 ms
M = 4.0 MHz M = 8.0 MHz
OFF
OFF
2.048 ms
1.024 ms
8.1920 ms
4.096 ms
32.768 ms
16.384 ms
131.072 ms 65.536 ms
524.288 ms 262.144 ms
1.048 s
524.288 ms
2.097 s
1.048576 s
Advance Information
MOTOROLA
Clock Module
MC68HC812A4 — Rev. 3.0
165