MC68HC812A4 Datasheet, PDF (157/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Clock Module
Functional Description
longer being executed in the intended sequence; thus, a system reset is
initiated. Three control bits allow selection of seven COP timeout
periods. When COP is enabled, sometime during the selected period the
program must write $55 and $AA (in this order) to the COPRST register.
If the program fails to do this, the part resets. If any value other than $55
or $AA is written, the part resets.
10.5.2 Real-Time Interrupt
There is a real-time (periodic) interrupt (RTI) available to the user. This
interrupt occurs at one of seven selected rates. An interrupt flag and an
interrupt enable bit are associated with this function. The rate select has
three bits.
10.5.3 Clock Monitor
The clock monitor circuit is based on an internal resistor-capacitor (RC)
time delay. If no MCU clock edges are detected within this RC time
delay, the clock monitor can generate a system reset. The clock monitor
function is enabled/disabled by the CME control bit in the COPCTL
register. This timeout is based on an RC delay so that the clock monitor
can operate without any MCU clocks.
CME enables clock monitor.
1 = Slow or stopped clocks (including the STOP instruction) cause
a clock reset sequence.
0 = Clock monitor is disabled. Slow clocks and STOP instruction
may be used.
Clock monitor timeouts are shown in Table 10-1.
Table 10-1. Clock Monitor Timeouts
Supply
5 V ± 10%
3 V ± 10%
Range
2–20 µs
5–100 µs
Advance Information
MOTOROLA
Clock Module
MC68HC812A4 — Rev. 3.0
157