MC68HC812A4 Datasheet, PDF (308/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

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The BDM control logic communicates with an external host development
system serially, via the BKGD pin. This single-wire approach minimizes
the number of pins needed for development support.
17.4.1 BDM Serial Interface
The BDM serial interface requires the external controller to generate a
falling edge on the BKGD pin to indicate the start of each bit time. The
external controller provides this falling edge whether data is transmitted
or received.
BKGD is a pseudo-open-drain pin that can be driven either by an
external controller or by the MCU. Data is transferred MSB first at 16
E-clock cycles per bit (nominal speed). The interface times out if 512
E-clock cycles occur between falling edges from the host. The hardware
clears the command register when this timeout occurs.
The BKGD pin can receive a high or low level or transmit a high or low
level. The following diagrams show timing for each of these cases.
Interface timing is synchronous to MCU clocks but asynchronous to the
external host. The internal clock signal is shown for reference in counting
cycles.
Figure 17-1 shows an external host transmitting a logic 1 or 0 to the
BKGD pin of a target M68HC12 MCU. The host is asynchronous to the
target so there is a 0-to-1 cycle delay from the host-generated falling
edge to where the target perceives the beginning of the bit time. Ten
target E cycles later, the target senses the bit level on the BKGD pin.
Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Since the
target does not drive the BKGD pin during this period, there is no need
to treat the line as an open-drain signal during host-to-target
transmissions.
MC68HC812A4 — Rev. 3.0
308
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