MC68HC812A4 Datasheet, PDF (199/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Standard Timer Module
Registers and Reset Initialization
PEDGE — Pulse Accumulator Edge Bit
PEDGE selects falling or rising edges on the PAI pin to increment the
counter.
In event counter mode (PAMOD = 0):
1 = Rising PAI edge increments counter
0 = Falling PAI edge increments counter
In gated time accumulation mode (PAMOD = 1):
1 = Low PAI input enables divided-by-64 clock to pulse
accumulator and trailing rising edge on PAI sets PAIF flag
0 = High PAI input enables divided-by-64 clock to pulse
accumulator and trailing falling edge on PAI sets PAIF flag
NOTE: The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
To operate in gated time accumulation mode:
1. Apply logic 0 to the RESET pin.
2. Initialize registers for pulse accumulator mode test.
3. Apply appropriate level on PAI pin.
4. Enable the timer.
CLK1 and CLK0 — Clock Select Bits
CLK1 and CLK0 select the timer counter input clock as shown in
Table 12-4.
Table 12-4. Clock Selection
CLK[1:0]
00
01
Timer Counter Clock⁽¹⁾
Timer prescaler clock⁽²⁾
PACLK
10
P-----A2----C5---6-L---K---
11
P-6---5-A---,-C-5---3L---6K---
1. Changing the CLKx bits causes an immediate change in the timer counter clock input.
2. When PAE = 0, the timer prescaler clock is always the timer counter clock.
Advance Information
MOTOROLA
Standard Timer Module
MC68HC812A4 — Rev. 3.0
199