MC68HC812A4 Datasheet, PDF (266/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Serial Peripheral Interface (SPI)
15.5 Register Map
NOTE:
The register block can be mapped to any 2-Kbyte boundary within the
standard 64-Kbyte address space. The register block occupies the first
512 bytes of the 2-Kbyte block. This register map shows default
addressing after reset.
Addr.
Register Name
Bit 7
6
5
SPI 0 Control ^Read: _SPIE
$00D0 Register 1 (SP0CR1) Write:
See page 273. _{Reset: 0}
SPE SWOM
0
0
SPI 0 Control ^{Read: 0}
0
0
$00D1 Register 2 (SP0CR2) Write:
See page 275. _{Reset: 0}
0
0
SPI Baud Rate Register ^{Read: 0}
0
0
$00D2
(SP0BR) Write:
See page 276. _{Reset: 0}
0
0
SPI Status Register ^{Read: SPIF WCOL}
0
$00D3
(SP0SR) Write:
See page 277. _{Reset: 0}
0
0
SPI Data Register ^Read: _{Bit 7}
6
5
$00D5
(SP0DR) Write:
See page 278. _Reset:
Port S Data Register ^Read: _PS7
PS6
PS5
$00D6
(PORTS) Write:
See page 219. _Reset:
$00D7
Port S Data Direction
Register (DDRS)
See page 220.
Read:
Write:
Reset:
DDRS7
0
DDRS6
0
DDRS5
0
= Unimplemented
4
MSTR
0
0
0
0
3
CPOL
0
PUPS
1
0
0
0
MODF
0
0
0
4
3
Unaffected by reset
PS4
PS3
Unaffected by reset
DDRS4 DDRS3
0
0
2
CPHA
1
RDS
0
SPR2
0
0
0
2
PS2
DDRS2
0
1
SSOE
0
0
0
SPR1
0
0
0
1
PS1
DDRS1
0
Bit 0
LSBF
0
SPC0
0
SPR0
0
0
0
0
PS0
DDRS0
0
Figure 15-2. SPI Register Map
15.6 Functional Description
The SPI allows full-duplex, synchronous, serial communication between
the MCU and peripheral devices, including other MCUs. In master mode,
the SPI generates the synchronizing clock and initiates transmissions. In
MC68HC812A4 — Rev. 3.0
266
Serial Peripheral Interface (SPI)
Advance Information
MOTOROLA