MC68HC812A4 Datasheet, PDF (47/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Register Block
Register Map
Addr.
Register Name
Bit 7
Port H Key Wakeup
Read:
KWIFH7
$0027 Flag Register (KWIFH) Write:
See page 148. _{Reset: 0}
Port J Data Register ^Read: _PJ7
$0028
(PORTJ) Write:
See page 148. _{Reset: 0}
$0029
Port J Data Direction
Register (DDRJ)
See page 149.
Read:
Write:
Reset:
DDRJ7
0
$002A
Port J Key Wakeup
Interrupt Enable
Register (KWIEJ)
See page 149.
Read:
Write:
Reset:
KWIEJ7
0
Port J Key Wakeup Flag ^Read: _KWIFJ7
$002B
Register (KWIFJ) Write:
See page 150. _{Reset: 0}
$002C
Port J Key Wakeup
Read:
KPOLJ7
Polarity Register Write:
(KPOLJ) See page 150. _{Reset: 0}
$002D
Port J Key Wakeup
Pullup/Pulldown Select
Register (PUPSJ)
See page 151.
Read:
Write:
Reset:
PUPSJ7
0
Port J Key Wakeup
$002E
Pullup/Pulldown Enable
Register (PULEJ)
See page 152.
Read:
Write:
Reset:
PULEJ7
0
$002F
Reserved
R
6
KWIFH6
0
PJ6
0
DDRJ6
0
KWIEJ6
0
KWIFJ6
0
KPOLJ6
0
PUPSJ6
0
PULEJ6
0
R
5
KWIFH5
0
PJ5
0
DDRJ5
0
KWIEJ5
0
KWIFJ5
0
KPOLJ5
0
PUPSJ5
0
PULEJ5
0
R
4
KWIFH4
0
PJ4
0
DDRJ4
0
KWIEJ4
0
KWIFJ4
0
KPOLJ4
0
PUPSJ4
0
PULEJ4
0
R
3
KWIFH3
0
PJ3
0
DDRJ3
0
KWIEJ3
0
KWIFJ3
0
KPOLJ3
0
PUPSJ3
0
PULEJ3
0
R
2
KWIFH2
0
PJ2
0
DDRJ2
0
KWIEJ2
0
KWIFJ2
0
KPOLJ2
0
PUPSJ2
0
PULEJ2
0
R
1
KWIFH1
0
PJ1
0
DDRJ1
0
KWIEJ1
0
KWIFJ1
0
KPOLJ1
0
PUPSJ1
0
PULEJ1
0
R
Bit 0
KWIFH0
0
PJ0
0
DDRJ0
0
KWIEJ0
0
KWIFJ0
0
KPOLJ0
0
PUPSJ0
0
PULEJ0
0
R
Port F Data Register ^{Read: 0}
$0030
(PORTF) Write:
See page 130. _{Reset: 0}
PF6
PF5
0
0
Port G Data Register ^{Read: 0}
$0031
(PORTG) Write:
See page 130. _{Reset: 0}
0
Bit 5
0
0
= Unimplemented
PF4
PF3
PF2
PF1
PF0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
R = Reserved
U = Unaffected
Figure 2-1. Register Map (Sheet 4 of 15)
Advance Information
MOTOROLA
Register Block
MC68HC812A4 — Rev. 3.0
47