MC68HC812A4 Datasheet, PDF (319/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

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Instruction Tagging
17.5.5 BDM CCR Holding Register
Address: $FF06
Bit 7
6
5
4
3
2
1
Read:
CCR7
Write:
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
Reset: 0
0
0
0
0
0
0
Figure 17-9. BDM CCR Holding Register (CCRSAV)
Bit 0
CCR0
0
This register preserves the content of the CPU12 CCR while BDM is
active.
17.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. Tagging information is latched on the falling edge of ECLK
along with program information as it is fetched. Tagging is allowed in all
modes. Tagging is disabled when BDM becomes active and BDM serial
commands cannot be processed while tagging is active.
TAGHI is a shared function of the BKGD pin.
TAGLO is a shared function of the PE3/LSTRB pin, a multiplexed I/O
pin. For 1/4 cycle before and after the rising edge of the E-clock, this pin
is the LSTRB driven output.
TAGLO and TAGHI inputs are captured at the falling edge of the E-clock.
A logic 0 on TAGHI and/or TAGLO marks (tags) the instruction on the
high and/or low byte of the program word that was on the data bus at the
same falling edge of the E-clock.
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MC68HC812A4 — Rev. 3.0
319