MC68HC812A4 Datasheet, PDF (167/342 Pages) Motorola, Inc – 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include

Advance Information — MC68HC812A4
Section 11. Phase-Lock Loop (PLL)
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
11.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
11.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.6 Registers and Reset Initialization . . . . . . . . . . . . . . . . . . . . . .171
11.6.1 Loop Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
11.6.2 Reference Divider Registers . . . . . . . . . . . . . . . . . . . . . . .172
11.6.3 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
11.2 Introduction
The phase-lock loop (PLL) allows slight adjustments in the frequency of
the MCU. The smallest increment of adjustment is ± 9.6 kHz to the
output frequency (F_Out) rate assuming an input clock of 16.8 MHz
(OSCXTAL) and a reference divider set to 1750. Figure 11-1 shows the
PLL dividers and a portion of the clock module and Figure 11-2 provides
a register map.
Advance Information
MOTOROLA
Phase-Lock Loop (PLL)
MC68HC812A4 — Rev. 3.0
167