SH7708 Datasheet, PDF (99/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Pipeline Sequence:
Instruction n
IF
Instruction n + 1
Instruction n + 2
Detection Order:
ID EX MA WB
TLB miss (data access)
IF ID EX MA WB
TLB miss (instruction access)
IF ID EX MA WB
RIE (reserved instruction exception)
TLB miss (instruction n+1)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection
Handling Order:
Program Order:
TLB miss (instruction n)
1
Re-execution of instruction n
TLB miss (instruction n + 1)
2
Re-execution of instruction n + 1
RIE (instruction n + 2)
3
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
Figure 4.2 Example of Acceptance Order of General Exceptions
All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the
delayed branch instruction. A completion type exception detected in a delayed branch instruction or
delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers to
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