SH7708 Datasheet, PDF (341/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 7—Carry Flag (CF): Status flag that indicates that a carry has occurred. CF is set to 1 when a
count-up to R64CNT or RSECCNT occurs. A count register value read at this time cannot be
guaranteed; another read is required.
Bit 7: CF
0
1
Description
No count up of R64CNT or RSECCNT.
Clearing condition: When 0 is written to CF
value)
Count up of R64CNT or RSECCNT.
Setting condition: When 1 is written to CF
(Initial
Bits 6, 5, 2, and 1—Reserved: These bits always read 0. The write value should always be 0.
Bit 4—Carry Interrupt Enable Flag (CIE): When the carry flag (CF) is set to 1, the CIE bit
enables interrupts.
Bit 4: CIE
0
1
Description
A carry interrupt is not generated when the CF flag is set to 1
value)
A carry interrupt is generated when the CF flag is set to 1
(Initial
Bit 3—Alarm Interrupt Enable Flag (AIE): When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
Bit 3: AIE
0
1
Description
An alarm interrupt is not generated when the AF flag is set to 1
(Initial
value)
An alarm interrupt is generated when the AF flag is set to 1
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in an alarm register
(only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to 0
by writing 0, but retains its previous value if 1 is written.
Bit 0: AF
Description
0
Clock/counter and alarm register have not matched since last reset to 0.
Clearing condition: When 0 is written to AF
(Initial value)
1
Setting condition: Clock/counter and alarm register have matched (only
registers with ENB set)*
Note: Contents do not change when 1 is written to AF.
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