SH7708 Datasheet, PDF (608/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Appendix B Control Registers
B . 1 Register Address Map
The address map of memory-mapped control registers is shown in Table B-1. The following
module abbreviations are used.
MMU: Memory management unit
UBC: User break controller
CPG: Clock pulse generator
BSC: Bus state controller
RTC: Realtime clock
INTC: Interrupt controller
TMU: Timer unit
SCI: Serial communication interface controller
CAC: Cache
The Bus column shows the internal bus to which the control register is connected.
S: System bus, to which the CPU, cache, TLB, multiplier, and UBC are connected.
C: Cache bus, to which the BSC and cache are connected.
P: Peripheral bus, to which the BSC and peripheral modules (RTC, INTC, TMU, and SCI)
are connected.
The Size column shows the register size in bits.
The Access Size column shows the size used when the control register is accessed (read or written).
If a size other than that indicated is used in an access, the result will be incorrect.
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